1. Field of the Invention
The present invention relates to an LSI circuit, and in particular, to a CMOS or Bi-CMOS logic product circuit.
This application is based on Japanese Patent Application Nos. Hei 11-182513 and Hei 11-218204, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Of conventional logic product circuits comprising CMOSs or Bi-CMOSs, a four-input NAND circuit provides a transistor array in which four transistors are aligned in a line and are connected between output terminals of the four-input NAND circuit and GND.
The four input terminals of the four-input NAND circuit are connected to the inputs (gates) to four transistors. When signals at an H level are input to all the input terminals and all four transistors are turned on, the entire transistor array becomes conductive, the output terminals are connected to GND, and the output terminals are set to an L level. Thus, this circuit functions as a NAND circuit.
Other conventional four-input NAND circuits increase their electric current driving performance of their outputs by connecting a plurality of transistor arrays in parallel between the output terminals and GND. When an electric current is supplied at the same time to a certain number n of transistor arrays provided in parallel, n times the electric current output from the single transistor array can be gained.
The structure of the four-input NAND circuit will be explained with reference to FIG. 5. In this figure, INA, INB, INC, and IND are inputs to the four-input NAND circuit, and OUT is an output from the four-input NAND circuit.
QP51, QP52, QP53, and QP54 are P-channel transistors (hereinafter referred to as Pch transistors), and QN51, QN52, . . . , QN59, QN5A, QN5B, and QN5C are N-channel transistors (hereinafter referred to as Nch transistors).
The Pch transistors QP51 to QP54 are connected between a power source voltage Vdd and an output terminal OUT in a parallel manner. That is, the sources of QP51 to QP54 are connected to the power source voltage Vdd, and the drains of QP51 to QP54 are connected to the output terminal OUT. The gates of QP51 to QP54 are connected to four input terminals INA, INB, INC, and IND, respectively.
The Nch transistors QN51 to QN54 are connected in a line, forming a transistor array TA51. In the transistor array TA51, the source of QN51 is connected to the drain of QN52, the source of QN52 is connected to the drain of QN53, and the source of QN53 is connected to the drain of QN54.
This transistor array TA51 is connected between the output terminal OUT and GND. That is, the drain of QN51 is connected to the output terminal OUT, and the source of QN54 is connected to GND.
Similarly, the Nch transistors QN55 to QN58 form a transistor array TA52, which is connected between the output terminal OUT and GND. Further, the Nch transistors QN59 to QN5C form a transistor array TA53, which is also connected between the output terminal OUT and GND.
The input terminals INA, INB, INC, and IND are connected to the gate terminals of the Pch transistors QP51, P52, QP53, and QP54, respectively.
When the input terminal INA is set to the L level, QP51 is turned on and becomes conductive so that the source voltage Vdd is output from the output terminal OUT. Similarly, when the input terminals INB, INC, and IND are set to the L level, QP52, QP53, and QP54 are turned on and become conductive so that the source voltage Vdd is output from the output terminal OUT. This output from the output terminal OUT is at the H level.
When a least one of the input terminals INA, INB, INC, and IND is set to the L level, a signal at the H level is output from the output terminal OUT.
The input terminal INA is connected to the gates of the Nch transistors QN51, QN55, and QN59 which are the nearest to the output terminal OUT. The input terminal INB is connected to the gates of Nch transistors QN52, QN56, and QN5A. The input terminal INC is connected to the gates of Nch transistors QN53, QN57, and QN5B. The input terminal IND is connected to the gates of the Nch transistors QN54, QN58, and QN5C which are the nearest to GND.
When the input terminal INA is set to the L level and the input terminals INB, INC, and IND are set to the H level, the Nch transistors QN51, QN55, and QN59 to which the input terminal INA is connected are turned off, the Nch transistors QN52, QN56, and QN5A to which the input terminal INB is connected, the Nch transistors QN53, QN57, and QN5B, and the Nch transistors QN54, QN58, and QN5C to which the input terminal IND is connected are turned on.
In this situation, because the transistor array TA51 includes the Nch transistor QN51 which has been turned off, the entire transistor array TA51 has been turned off. Similarly, because the transistor array TA52 includes the Nch transistor QN55 which has been turned offOFF, the entire transistor array TA52 has been turned off. Further, because the transistor array TA53 includes the Nch transistor QN59 which has been turned off, the entire transistor array TA53 has been turned off.
Because the transistor arrays TA51, TA52, and TA53 which are provided in parallel to each other between the output terminal OUT and GND have been turned off, the output terminal OUT is not connected to GND. Because the input terminal INA is at the L level, the Pch transistor QP51 has been turned on so that the source voltage Vdd is connected to the output terminal OUT.
Accordingly, when the input terminal INA is set to the L level and the input terminals INB, INC, and IND are set to the H level, the output terminal OUT outputs a signal at the H level.
When all the input terminals INA, INB, INC, and IND are set to the H level, the Nch transistors QN51, QN55, QN59, QN52, QN56, QN5A, QN53, QN57, QN5B, QN54, QN58, and QN5C are turned on. That is, the transistor arrays TA51, TA52, and TA53 become conductive so that the output terminal OUT is connected to GND. On the other hand, because all the input terminals INA to IND are at the H level, all the Pch transistors QP51 to QP54 have been turned off, and the source voltage Vdd is not connected to the output terminal OUT.
Accordingly, when all the input terminals INA, INB, INC, and IND are set to the H level, the output terminal OUT outputs a signal at the L level.
Next, the operation of this conventional art will be explained with reference to the operation timing chart of FIG. 6. Before the point of time t61, because the input terminal INA is at the L level and INB to IND are at the H level, the output terminal OUT is at the H level.
At the point of time t61, when the input terminal INA is inverted from the L level to the H level while maintaining the input terminals INB to IND at the H level, that is, when all the input terminals INA to IND are set to the H level, the output terminal OUT varies from the H level to the L level in the period tpdA between t61 and t62.
At the point of time t63, when the input terminal IND is inverted from the H level to the L level while maintaining the input terminals INA to INC at the H level, the output terminal OUT varies from the L level to the H level in the period tpdD between t63 and t64.
At the point of time t65, when the input terminal IND is inverted from the L level to the H level while maintaining the input terminals INA to INC at the H level, the output terminal OUT varies from the H level to the L level in the period tpdD between t65 and t66.
As another conventional technique, a five-input NAND circuit shown in the circuit diagram of FIG. 7 is known. In this circuit, each of the transistor arrays TA1 to TA4 comprises five Nch transistors connected in a line. The gates of the five Nch transistors are connected to input terminals INA to INE, respectively.
FIG. 10 shows the layout of the circuit on an IC. On the IC, the transistor arrays TA1 to TA4 are aligned in a line.
In the transistor array TA1, the Nch transistors are arranged in the order of QN1, QN2, QN3, Qn4, and Qn5 from the left of FIG. 10. In the transistor array TA2, the Nch transistors are arranged in the order of QN10, QN9, QN8, Qn7, and Qn6 from the left of FIG. 10. In the transistor array TA3, the Nch transistors are arranged in the order of QN11, QN12, QN13, Qn14, and Qn15 from the left of FIG. 10. In the transistor array TA4, the Nch transistors are arranged in the order of QN20, QN19, QN18, Qn17, and Qn16 from the left of FIG. 10. That is, the QN1 to QN20 are aligned in a line. The transistor arrays TA1 to TA4 are formed in separated well areas.
In the transistor array TA1, the source area of the transistor QN5 is connected via an aluminum first-layer connection to a GND aluminum first-layer connection. The drain area of the QN5 is in the same diffusion area as the source area of the QN4 adjacent to the QN5. The drain area of QN4 is in the same diffusion area as the source area of the QN3 adjacent to the QN4. The drain area of the QN3 is connected to the source area of the next QN2 via two parallel aluminum first-layer connections.
The drain area of the QN2 is in the same diffusion area as the source area of the adjacent QN1. The drain area of the QN1 is connected to the output terminal OUT via the aluminum first-layer connection.
The drain area of the QN6 in the transistor array TA2 is connected to the drain area of the QN11 in the adjacent transistor array TA3 by two aluminum first-layer connections. Further, these connections are connected to the output terminal OUT by an aluminum first-layer connection.
In the transistor array TA2, the source area of the QN6 is in the same diffusion area as the drain area of the adjacent QN7. The source area of the QN7 is in the same diffusion area as the drain area of the adjacent QN8. The source area of the QN8 is connected to the drain area of the adjacent QN9 via two aluminum first-layer connections. The source area of the QN9 is in the same diffusion area as the drain area of the adjacent QN10. The source area of the QN10 is connected to the GND aluminum first-layer connection via an aluminum first-layer connection.
The arrangement in the transistor array TA3 is similar to that in the transistor array TA1, and the arrangement in the transistor array TA4 is similar to that in the transistor array TA2.
FIG. 11 is the timing chart showing the operation of the above-mentioned circuit. When at the point of time t51 the input terminal INE is inverted from the H level to the L level, the output terminal OUT varies from the L level to the H level between t51 and t52. When at the point of time t53 the input terminal INE is inverted from the L level to the H level, the output terminal OUT varies from the H level to the L level between t53 and t54.
In the conventional four-input NAND circuit which comprises CMOSs shown in FIG. 5, when only the input terminal INA is set to the L level and the other INB to IND are set to the H level, only the Pch transistor QP51 is turned on, and the other QP52 to QP54 are turned off. Further, the Nch transistors QN51, QN55, and QN59 are turned off, and the other QN52 to QN54, QN56 to QN58, and QN5A to QN5C are turned on.
Because the Pch transistor QP51 has been turned on, the output terminal OUT is at the H level. All the areas connected to the output terminal OUT are at the H level. These areas are full of positive electric charge. Specifically, the areas to the output terminal OUT are the connection portions of the sources and drains of the Pch transistors QP51 to QP54, and the connected portions of the drains of the Nch transistors QN51, QN55, and QN59. Positive electric charge is filled to the junction capacities of these connected portions.
When, while setting the input terminals INB to IND at the H level, only the input terminal INA is inverted from the L level to the H level, the Pch transistors QP51 is turned off, and the Nch transistors QN51, QN55, and QN59 are turned on, so that the output terminal OUT is changed from the H level to the L level.
At that time, the positive electric charge, which has been stored to the junction capacities at the drains of QN51, QN55 and QN59 and at the drains of QP51, QP52, QP53, and QP54, is discharged. The amount of discharge is in proportion to the total junction capacities. When the electric charge stored atone of terminals of the transistor, that is, the drain or the source, is 0.5, the electric discharge caused by changing the input terminal INA from the L level to the H level becomes 0.5xc3x97(3+4)=3.5.
The time tpdA required to invert the output terminal OUT from the H level to the L level, that is, the output level changing time is in proportion to the electric discharge of 3.5.
On the other hand, when the input terminals INA to INC are set to the H level and only IND is set to the L level, only the Pch transistor QP54 is turned on, and the other QP51 to QP53 are turned off. Further, the Nch transistors QN54, QN58, and QN5C are turned off, and the QN51 to QN53, QN55 to Qn57, and QN59 to QN5B are turned on.
In this situation, the output terminal OUT is set to the H level by the Pch transistor QP54. All the areas connected to the output terminal OUT are at the H level. These areas are full of positive electric charge. Specifically, the areas to the output terminal OUT are the connection portions of the sources and drains of the Pch transistors QP51 to QP54, and the connected portions of the drains and sources of the Nch transistors QN51 to QN53, QN55 to QN57, and QN59 to QN5B, and the connected portions of the drains of the QN54, QN58, and QN5C. Positive electric charge is applied to the junction capacities of these connected portions.
When, while setting the input terminals INA to INC at the H level, only the input terminal IND is inverted from the L level to the H level, the Pch transistors QP54 is turned off, and the Nch transistors QN54, QN58, and QN5C are turned on, so that the output terminal OUT is inverted from the H level to the L level.
At that time, the positive electric charge, which has been stored to the junction capacities at the drains and sources of QN51 to QN53, QN55 to QN57, and QN59 to QN5B, at the drains of the QN54, QN58, and QN5C, and at the drains of the QP51, QP52, QP53, and QP54, which are connected to the output terminal OUT, is discharged. In a manner similar to the fore-mentioned case, when the electric charge stored at one of terminals of the transistor is 0.5, the electric discharge becomes 0.5xc3x972xc3x973xc3x973+0.5xc3x97(3+4)=12.5.
The output level changing time tpdD of the output terminal OUT is in proportion to the electric discharge of 12.5.
That is, when the output terminal OUT is inverted from the H level to the L level, the electric charge and discharge differ from each other between the case in which the level of the input terminal connected to the transistor close to the output terminal OUT, e.g., INA is changed, and the case in which the level of the input terminal connected to the transistor close to the GND, e.g., IND is changed. Therefore, there is the problem that the output level changing times tpd at the output terminal OUT significantly differ.
In the example shown in FIG. 6, the output level changing time tpdD (from t63 to t64, and from t65 to t66) when the level of the input terminal IND is changed is approximately twice the output level changing time tpdA (from t61 to t62) when the level of the input terminal INA is changed.
In the five-input NAND circuit shown in FIG. 7, when, maintaining the INA to IND at the H level, only the INE is inverted from the L level to the H level, the electric charge, which is stored at the drains and sources of the Nch transistors QN1 to QN4, QN6 to QN9, QN11 to QN14, and QN16 to QN19 connected in lines and the drains of the QN5, QN10, QN15, and QN20, must be discharged. Further, the electric charge which is stored at the drains of the Pch transistors QP1 to QP5 must be discharged.
When the junction capacity of one of the terminals of the transistor, that is, the drain or the source, is 0.5, the junction capacity of the Nch transistors is 18, the junction capacity of the Pch transistor is 2.5, and the total of the junction capacities is 20.5, which correspond to 72 fF.
To the above-mentioned junction capacity, the capacity of 80fF of the aluminum first-layer connection with the length of 400 im, which is shown in FIG. 10, is added, and the total capacity is 152 fF.
Accordingly, when only the input terminal INE is inverted from the L level to the H level, the electric charge, stored to the total capacity of 152 fF, must be completely discharged. As shown in the timing chart of FIG. 11, there is the problem that the time tpd required to change the level at the output terminal OUT, depending on the level at the input terminal INE, is lengthened from t51 to t52 and from t53 to t54.
It is therefore an object of the present invention to provide a logic product circuit that prevents the output level changing time from being lengthened, even when the level at any of input terminals is changed.
In a first aspect of the present invention, the logic product circuit comprises: a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.
In the first aspect of the present invention, the numbers of the transistors in the respective rows are the same. The transistors are MOSFETs, or junction field effect transistors.
In a second aspect of the present invention, the logic product circuit comprises: a plurality of transistors arranged in a matrix; a plurality of input terminals; a single output transistor; and a single output terminal connected to the output transistor. The transistors in each column are connected in a line, forming a transistor array; the transistor arrays are connected in parallel so that the transistors form rows, one of the rows of the transistors is connected between the input to the output transistor and the ground, the other row of the transistors is connected between the output terminal and the ground, the input terminals are connected to the input to the transistors in all the columns; and the transistors to which each input terminal is connected are arranged in different rows.
In the second aspect of the present invention, the numbers of the transistors in the respective rows is the same. The transistors are MOSFETs, or junction field effect transistors. The output transistor is a bipolar transistor.
In a third aspect of the present invention, the logic product circuit comprises: a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output transistor, a single output terminal. The transistors in each column are connected in a line, forming a transistor array; the transistor arrays are connected in parallel between the output terminal and the ground; each of the input terminals is connected to the transistors in all the columns; and the transistors forming the transistor arrays neighbor each other on an IC.
In the third aspect of the present invention, the transistors forming the transistor array are N-channel MOS transistors. All the transistors in the transistor arrays are arranged in a single line on the IC, a connection from the output terminal is provided in the middle of the line of the transistors, and the terminals at the both ends of the line of the transistors are connected to the ground. Some of the neighboring transistors in the transistor arrays on the IC are connected without an aluminum connection. Further, some of the sources and drains of the transistors on the IC are within the same diffusion areas.
According to the present invention, when the level of one of the input terminals is changed, the junction capacities of the transistors are set so that the electric charge or discharge is made regular, decreasing a variation in the output level changing time.
Because the electric charge or discharge is made regular, the electric charge can be decreased, thereby shortening the output level changing time and accelerating switching of the outputs, as compared with the conventional technique.
Further, according to the IC layout of the present invention, when changing the output level, the electric charge or discharge can be decreased, thereby shortening the output level changing time and accelerating switching of the outputs.